In a conventional computer system a storage controller may be coupled to memory and a bus from which requests to write data to and/or read data from the memory may be received. When the storage controller receives such a request, the controller performs processing, such as checking for free buffers and translating an address associated with the request. During this time other requests may be prevented from accessing the bus. Further, in certain specifications, such as PCI, data transferred on the bus while writing data to and/or reading data from the memory may be disconnected along any boundary. Consequently, the storage controller of such a computer system may not provide for efficient data transfer.